Invention Grant
- Patent Title: Method to improve source/drain parasitics in vertical devices
- Patent Title (中): 在垂直设备中改善源极/漏极寄生效应的方法
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Application No.: US11800204Application Date: 2007-05-04
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Publication No.: US08258035B2Publication Date: 2012-09-04
- Inventor: Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
- Applicant: Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).
Public/Granted literature
- US20080274600A1 Method to improve source/drain parasitics in vertical devices Public/Granted day:2008-11-06
Information query
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