Invention Grant
- Patent Title: Method for fabricating chip elements provided with wire insertion grooves
- Patent Title (中): 具有电线插入槽的芯片元件的制造方法
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Application No.: US13103533Application Date: 2011-05-09
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Publication No.: US08258044B2Publication Date: 2012-09-04
- Inventor: Jean Brun , Dominique Vicard
- Applicant: Jean Brun , Dominique Vicard
- Applicant Address: FR Paris
- Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
- Current Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
- Current Assignee Address: FR Paris
- Agency: Oliff & Berridge, PLC
- Priority: FR1002080 20100518
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
The invention relates to a method for fabricating chip elements provided with a groove from devices formed on a wafer. The method comprises the steps consisting in, depositing a sacrificial film on the wafer so as to leave a central part of each device exposed and to cover an edge of the device at the level of which the groove is to be formed; applying a mold on the sacrificial film; injecting a hardenable material into the mold; hardening the hardenable material; dicing the wafer between the devices; and eliminating the sacrificial film.
Public/Granted literature
- US20110287606A1 METHOD FOR FABRICATING CHIP ELEMENTS PROVIDED WITH WIRE INSERTION GROOVES Public/Granted day:2011-11-24
Information query
IPC分类:
