Invention Grant
US08258053B2 Performance enhancement in transistors comprising high-K metal gate stack by reducing a width of offset spacers
有权
通过减小偏移间隔物的宽度，包括高K金属栅极叠层的晶体管的性能增强
- Patent Title: Performance enhancement in transistors comprising high-K metal gate stack by reducing a width of offset spacers
- Patent Title (中): 通过减小偏移间隔物的宽度，包括高K金属栅极叠层的晶体管的性能增强
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Application No.: US12900578Application Date: 2010-10-08
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Publication No.: US08258053B2Publication Date: 2012-09-04
- Inventor: Stephan Kronholz , Matthias Kessler , Andreas Kurz
- Applicant: Stephan Kronholz , Matthias Kessler , Andreas Kurz
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE102009047314 20091130
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/4763
Abstract:
In sophisticated semiconductor devices including transistors having a high-k metal gate electrode structure, disposable spacers may be provided on the encapsulating spacer element with a reduced width so as to not unduly increase a lateral offset of a strain-inducing material to be incorporated into the active region. For this purpose, a multi-layer deposition may be used in combination with a low pressure CVD process.
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