Invention Grant
US08258410B2 Construction of reliable stacked via in electronic substrates—vertical stiffness control method
有权
在电子基板中构建可靠的堆叠通孔 - 垂直刚度控制方法
- Patent Title: Construction of reliable stacked via in electronic substrates—vertical stiffness control method
- Patent Title (中): 在电子基板中构建可靠的堆叠通孔 - 垂直刚度控制方法
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Application No.: US12020534Application Date: 2008-01-26
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Publication No.: US08258410B2Publication Date: 2012-09-04
- Inventor: Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
- Applicant: Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Michael J. Buchenhorner; Vazken Alexanian
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K1/09
Abstract:
A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing.
Public/Granted literature
- US20090188705A1 Construction of Reliable Stacked Via in Electronic Substrates - Vertical Stiffness Control Method Public/Granted day:2009-07-30
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