Invention Grant
- Patent Title: Semiconductor device having tri-gate structure and manufacturing method thereof
- Patent Title (中): 具有三栅结构的半导体器件及其制造方法
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Application No.: US12470030Application Date: 2009-05-21
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Publication No.: US08258562B2Publication Date: 2012-09-04
- Inventor: Takashi Izumida , Takahisa Kanemura , Nobutoshi Aoki
- Applicant: Takashi Izumida , Takahisa Kanemura , Nobutoshi Aoki
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2008-134580 20080522
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
A semiconductor device of an example of the invention comprises a memory cell and a select gate transistor provided for the memory cell. A gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor.
Public/Granted literature
- US20090289293A1 SEMICONDUCTOR DEVICE HAVING TRI-GATE STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2009-11-26
Information query
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