A technique which prevents cracking in a solder resist layer covering an interposer surface between external coupling terminals of an interconnection substrate, thereby reducing the possibility of interconnect wire disconnection resulting from such cracking. A semiconductor package is mounted over an interconnection substrate. An underfill resin layer seals the space between the semiconductor package and the interconnection substrate. External coupling terminals, interconnect wires and a solder resist layer are formed over the surface of an interposer (constituent of the semiconductor package) where the semiconductor chip is not mounted. In an area where an interconnect wire passing between two neighboring ones of the external coupling terminals intersects with a line connecting the centers of the two external coupling terminals, the interconnect wire is not covered by the solder resist layer.