The present invention relates to a circuit for generating a clock signal. The circuit comprises a current source to generate a reference current and provide a first voltage V1, a first current generator to generate a first mirror current during a first half cycle based on the reference current, a first capacitor including a first end, and a first transistor having a first threshold voltage VTH1. The first transistor includes a gate to receive the first voltage V1, a drain coupled to the first current generator and a source coupled to the first end of the first capacitor so as to allow the first mirror current to charge the first capacitor during the first half cycle, wherein the period of the first half cycle is a function of the first bias voltage V1 minus the first threshold voltage VTH1.