A phase locked loop (PLL) includes a clock generating circuit, a first phase detecting circuit, a first loop filter, a first VCO, a first mixer and a control circuit. The clock generating circuit generates a first clock signal. The first phase detecting circuit detects a phase difference between an input data signal and a feedback signal and generates a detection output signal according to the phase difference. The first loop filter, coupled to the first phase detecting circuit, generates a first VCO control signal according to the detection output signal. The first mixer, coupled to the first VCO and the clock generating circuit, mixes the output data signal and the first clock signal to generate the feedback data signal. The control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal according to the first VCO control signal to calculate a gain of the first VCO.