The display device includes a display cell including liquid crystals and a matrix of electrodes arranged in lines and columns in a closed cavity. The lines and columns define display cell pixels. The display device includes a control circuit for lines and columns for display of data on the display cell. In complete display mode, all lines and columns are addressed at several voltage levels by successive line-by-line multiplexing. In low power partial display mode, two groups of adjacent lines are joined so they are each controlled by a respective line control signal from the control circuit. The N lines and groups of lines are simultaneously addressed in active manner at two voltage levels. N line control signals include a series of N-bit binary line words that change every determined period of time, T, so 2N combinations of binary line words are present in each successive cycle of length 2N·T.