Invention Grant
- Patent Title: Fabrication method of semiconductor integrated circuit device
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Application No.: US13399684Application Date: 2012-02-17
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Publication No.: US08259295B2Publication Date: 2012-09-04
- Inventor: Norio Watanabe
- Applicant: Norio Watanabe
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP2004-015718 20040123
- Main IPC: G01N21/00
- IPC: G01N21/00

Abstract:
In the fabrication of a semiconductor integrated circuit device, a 2D-3D inspection technique for solder printed on a substrate is provided which permits easy preparation of data and easy visual confirmation of a defective portion. In a substrate inspecting step, first, a 3D inspection is performed, followed by execution of 2D inspection, whereby a 2D picked-up image of the portion of a pad determined to be defective can be displayed on a larger scale simultaneously with the end of inspection, thereby providing an environment for efficient visual confirmation of the defect. Further, by subjecting a raw substrate to measurement at the time of preparing inspection data, a relation between an original height measurement reference generated automatically by the inspection system and the height of a pad upper surface is checked, whereby it is possible to measure the height and volume of printed solder based on the pad upper surface.
Public/Granted literature
- US20120149136A1 FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2012-06-14
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