Technologies are described herein for allocating interrupts within a multiprocessor computing system. Information communicated to an interrupt controller module can support allocating interrupt response resources so as to maintain processor affinity for interrupt service routines. This affinity can support caching efficiency by executing a specific interrupt handler on a processor that previously executed that interrupt handler. The caching efficiency may be balanced against the benefits of assigning execution of the interrupt hander to another processor that is currently idle or currently processing a lower priority task.