A non-volatile semiconductor memory is disclosed comprising a first memory device having a memory array including a plurality of memory segments, and a data register for storing write data prior to being written to one of the memory segments. A memory controller comprises a microprocessor for executing access commands received from a host. Interface circuitry generates control signals that enable the microprocessor to communicate with the first memory device. Power fail circuitry transmits a flush command to the first memory device through the interface circuitry in response to a power fail signal, wherein the first memory device responds to the flush command by transferring the write data stored in the data register to the memory segment.