A data processor includes a cache memory control section which includes: a hit/miss determination section which is supplied with a request for data processing to determine whether data to be processed is present in a cache memory and outputs a cache hit/miss determination result and, if having determined that the data is not present in the cache memory, feeds a read command to make an upper memory control section read the data from the upper memory; a FIFO storage which stores the cache hit/miss determination result and the in-block read position information according to a FIFO system; and a cache memory read/write section which reads the hit/miss determination result and the in-block read position information from the FIFO storage and reads the data from the cache memory, or writes the data from the upper memory control section into the cache memory and outputs the data.