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US08261166B2 Node processor for use with low density parity check decoder using multiple variable node degree distribution codes 有权
节点处理器用于使用多个可变节点度分布码的低密度奇偶校验解码器

Node processor for use with low density parity check decoder using multiple variable node degree distribution codes
Abstract:
A decoding system for use with different degree parity constraint nodes and highly parallel processing operates by passing messages to variable nodes based on updated states of first and second check nodes, processing messages from the variable nodes and updating states of first and second check nodes in a decoder with Z processors that operate in parallel, further processing the updated state information for the second check nodes to coordinate the states of N=Z/z sets of second check nodes, where z is the number of bits associated with the second check nodes, and repeating the process utilizing the coordinated states of the second check nodes as the updated states of the second check nodes.
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