Systems and methods for determining clock-path connection delays are described. The systems include a memory configured to store information, and a processor coupled to the memory. The processor determines whether a clock delay applied to a first storage node changes independently of a clock delay applied to a second storage node. The processor determines ideal path delay changes to apply to the first node upon determining that the delay applied to the first node changes independently of the delay applied to the second node. The processor further determines clock path connection delay changes to apply to a group or a collection of the first and second nodes upon determining that the delay applied to the first node cannot or should not change independently of the delay applied to the second node. Such grouping or collections help resolve any conflicts between the first and second nodes and improves processor efficiency by applying the methods to the group or collection instead of each of the individual nodes. Further, the processor considers restrictions based on the granularity of delay options and/or the range of delay options on clock paths.