A method for fabricating a semiconductor device includes providing a semiconductor substrate including a memory cell region and peripheral circuit regions. Gate electrodes including gate conductive patterns and capping patterns are formed on the memory cell region and the peripheral circuit regions. An interlayer dielectric covering the gate electrodes is formed. The interlayer dielectric is patterned to form first contact holes exposing the semiconductor substrate along side of the gate electrode in the memory cell region and second contact holes exposing a portion of the capping pattern in the peripheral circuit region such that a bottom surface of the second contact hole is spaced apart from a top surface of the gate conductive pattern. A first plug conductive layer is filled in the first contact holes and a second plug conductive layer is filled in the second contact holes. A planarizing process is performed to expose the capping patterns such that first contact plugs are formed in the memory cell region and second contact plugs are formed in the peripheral circuit region.