Invention Grant
- Patent Title: Hybrid planarFET and FinFET provided on a chip
- Patent Title (中): 混合平面FET和FinFET提供在芯片上
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Application No.: US12662498Application Date: 2010-04-20
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Publication No.: US08269271B2Publication Date: 2012-09-18
- Inventor: Toshiyuki Iwamoto , Gen Tsutsui
- Applicant: Toshiyuki Iwamoto , Gen Tsutsui
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2009-104723 20090423
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119
Abstract:
A semiconductor device includes: a FinFET (Fin Field Effect Transistor); and a PlanarFET (Planar Field Effect Transistor). The FinFET is provided on a chip. The PlanarFET is provided on the chip. A second gate insulating layer of the PlanarFET is thicker than a first gate insulating layer of the FinFET.
Public/Granted literature
- US20100270621A1 Semiconductor device and method of manufacturing the semiconductor device Public/Granted day:2010-10-28
Information query
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