Invention Grant
- Patent Title: High speed, low power consumption, isolated analog CMOS unit
- Patent Title (中): 高速，低功耗，隔离模拟CMOS单元
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Application No.: US12862163Application Date: 2010-08-24
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Publication No.: US08269279B2Publication Date: 2012-09-18
- Inventor: Jun Cai
- Applicant: Jun Cai
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Agency: Hiscock & Barclay, LLP
- Main IPC: H01L27/01
- IPC: H01L27/01 ; H01L27/12 ; H01L31/0392
Abstract:
A semiconductor device including: a low threshold PMOS device formed over an N-type region, the source and drain of the low threshold PMOS formed in P-regions surrounded by N-regions; a low threshold NMOS device formed in a P-type region, the source and drain of the low threshold NMOS formed in N-regions surrounded by P-regions; first and second substrate bias generators, each connected to one of the low threshold devices for generating a substrate bias; a voltage source for generating substrate bias during a standby mode to reduce leakage current; wherein a low voltage threshold is established by the source and drain regions of the low threshold devices and their respective surrounding regions of opposite polarity.
Public/Granted literature
- US20100315155A1 HIGH SPEED, LOW POWER CONSUMPTION, ISOLATED ANALOG CMOS UNIT Public/Granted day:2010-12-16
Information query
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