Invention Grant
US08269523B2 VLSI layouts of fully connected generalized networks 有权
完全连接的广义网络的VLSI布局

  • Patent Title: VLSI layouts of fully connected generalized networks
  • Patent Title (中): 完全连接的广义网络的VLSI布局
  • Application No.: US12601275
    Application Date: 2008-05-22
  • Publication No.: US08269523B2
    Publication Date: 2012-09-18
  • Inventor: Venkat Konda
  • Applicant: Venkat Konda
  • Applicant Address: US CA San Jose
  • Assignee: Konda Technologies Inc.
  • Current Assignee: Konda Technologies Inc.
  • Current Assignee Address: US CA San Jose
  • International Application: PCT/US2008/064605 WO 20080522
  • International Announcement: WO2008/147928 WO 20081204
  • Main IPC: H03K19/177
  • IPC: H03K19/177
VLSI layouts of fully connected generalized networks
Abstract:
In accordance with the invention, VLSI layouts of generalized multi-stage networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation.The VLSI layouts presented are applicable to generalized multi-stage networks V(N1, N2, d, s), generalized folded multi-stage networks Vfold(N1, N2, d, s), generalized butterfly fat tree networks Vbft(N1, N2, d, s), generalized multi-link multi-stage networks Vmlink(N1, N2, d, s), generalized folded multi-link multi-stage networks Vfold-mlink(N1, N2, d, s), generalized multi-link butterfly fat tree networks Vmlink-bft(N1, N2, d, s), and generalized hypercube networks Vhcube(N1, N2, d, s) for s=1, 2, 3 or any number in general. The embodiments of VLSI layouts are useful in wide target applications such as FPGAs, CPLDs, pSoCs, ASIC placement and route tools, networking applications, parallel & distributed computing, and reconfigurable computing.
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