According to one embodiment, a semiconductor memory device comprises a memory cell array and a control circuit. The control circuit applies a certain potential difference to a selected one of the memory cells. The control circuit comprises a current mirror circuit, a reference current generating circuit, and a detecting circuit. The current mirror circuit produces a mirror current having a current value identical to that of a cell current flowing in the selected one of the memory cells. The reference current generating circuit produces a reference current, the reference current having a current value that differs from the current value of the mirror current by a certain current value. The detecting circuit detects transition of a resistance state of the selected one of the memory cells based on a magnitude relation of the mirror current and the reference current.