Invention Grant
- Patent Title: Flash memory array system including a top gate memory cell
- Patent Title (中): 包括顶栅存储单元的闪存阵列系统
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Application No.: US12962343Application Date: 2010-12-07
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Publication No.: US08270213B2Publication Date: 2012-09-18
- Inventor: Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
- Applicant: Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Main IPC: G11C16/12
- IPC: G11C16/12
Abstract:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
Public/Granted literature
- US20110122693A1 FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL Public/Granted day:2011-05-26
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