Invention Grant
US08270438B2 Apparatus and method of compensating for clock frequency and phase variations by processing packet delay values
有权
通过处理分组延迟值来补偿时钟频率和相位变化的装置和方法
- Patent Title: Apparatus and method of compensating for clock frequency and phase variations by processing packet delay values
- Patent Title (中): 通过处理分组延迟值来补偿时钟频率和相位变化的装置和方法
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Application No.: US13221722Application Date: 2011-08-30
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Publication No.: US08270438B2Publication Date: 2012-09-18
- Inventor: Charles F. Barry , Meenakshi S. Subramanian , Feng Frank Pan , Tian Alan Shen , Philip Kruzinski , Guochun George Zhao , DeviPrasad Natesan , David R. Jorgensen
- Applicant: Charles F. Barry , Meenakshi S. Subramanian , Feng Frank Pan , Tian Alan Shen , Philip Kruzinski , Guochun George Zhao , DeviPrasad Natesan , David R. Jorgensen
- Applicant Address: US CA Sunnyvale
- Assignee: Juniper Networks, Inc.
- Current Assignee: Juniper Networks, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Cooley LLP
- Main IPC: H04J3/06
- IPC: H04J3/06

Abstract:
An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.
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