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US08270501B2 Clocking architectures in high-speed signaling systems 有权
高速信号系统中的时钟架构

Clocking architectures in high-speed signaling systems
Abstract:
Clocking systems and methods are provided below that accurately clock per-pin data transfers of input/output (IO) circuits of integrated circuit devices. These multiplexer-based clock selection systems use a dedicated multiplexer to receive clock signals from multiple mixer circuits and in turn to provide a selected reference clock signal for use by an interface circuit in transferring data to other integrated circuit devices. The timing of the selected reference clock signal is synchronized with the data signals to provide optimal sampling of the data signals. The multiplexer-based clock selection system is for use in memory interfaces of high-speed signaling systems for example.
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