Invention Grant
- Patent Title: Fabrication system of semiconductor integrated circuit, fabrication device, fabrication method, integrated circuit and communication system
- Patent Title (中): 半导体集成电路制造系统,制造装置,制造方法,集成电路和通信系统
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Application No.: US12523834Application Date: 2008-11-14
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Publication No.: US08271117B2Publication Date: 2012-09-18
- Inventor: Takahiro Ichinomiya , Takashi Hashimoto
- Applicant: Takahiro Ichinomiya , Takashi Hashimoto
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: JP2007-302668 20071122
- International Application: PCT/JP2008/003329 WO 20081114
- International Announcement: WO2009/066431 WO 20090528
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A manufacturing system which can restrain the margin of a semiconductor integrated circuit. The integrated circuit including a fixed circuit unit and a reconfigurable circuit unit outputs, to a configuration determining server, an operation time which was calculated by a detecting unit and a calculating unit. The configuration determining server, by using the operation time obtained from the integrated circuit, calculates performance data which indicates the characteristics of the fixed circuit unit, selects, based on the performance data, a piece of configuration information indicating a circuit configuration that is optimum for the processing of the reconfigurable circuit unit, and outputs the selected piece of configuration information. The integrated circuit builds a circuit in the reconfigurable circuit unit in accordance with the output piece of configuration information.
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