Invention Grant
- Patent Title: Testing state retention logic in low power systems
- Patent Title (中): 在低功率系统中测试状态保持逻辑
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Application No.: US12147428Application Date: 2008-06-26
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Publication No.: US08271226B2Publication Date: 2012-09-18
- Inventor: Krishna Chakravadhanula , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
- Applicant: Krishna Chakravadhanula , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F3/01 ; G06F3/06 ; G06F13/10
Abstract:
A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.
Public/Granted literature
- US20090326854A1 TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS Public/Granted day:2009-12-31
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