Invention Grant
- Patent Title: Simulation model of BT instability of transistor
- Patent Title (中): 晶体管BT不稳定性仿真模型
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Application No.: US11878196Application Date: 2007-07-23
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Publication No.: US08271254B2Publication Date: 2012-09-18
- Inventor: Akinari Kinoshita , Tomoyuki Ishizu
- Applicant: Akinari Kinoshita , Tomoyuki Ishizu
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2006-206203 20060728; JP2007-167655 20070626
- Main IPC: G01R31/34
- IPC: G01R31/34 ; G06F7/60 ; G06F17/50 ; G06F9/44 ; G06F9/445 ; G06G7/54 ; G06G7/52
Abstract:
A simulation model of BT instability of a transistor in a semiconductor integrated circuit, wherein a bias condition of at least one terminal among the drain terminal, the source terminal and the substrate terminal of the transistor is set up as an independent bias condition from other terminals; and then a model parameter of the transistor is changed in the set bias condition.
Public/Granted literature
- US20080027700A1 Simulation model of BT instability of transistor Public/Granted day:2008-01-31
Information query
