Invention Grant
- Patent Title: Method of calculating gate delay based on crosstalk effect due to capacitive coupling
- Patent Title (中): 基于电容耦合的串扰效应计算门延迟的方法
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Application No.: US12475544Application Date: 2009-05-31
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Publication No.: US08271255B2Publication Date: 2012-09-18
- Inventor: Tae II Bae , Young Hwan Kim , Jinwook Kim
- Applicant: Tae II Bae , Young Hwan Kim , Jinwook Kim
- Applicant Address: KR Pohang
- Assignee: Postech Academy-Industry Foundation
- Current Assignee: Postech Academy-Industry Foundation
- Current Assignee Address: KR Pohang
- Agency: Kile Park Goekjian Reed & McManus PLLC
- Priority: KR10-2009-0045655 20090525
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455 ; G06G7/62

Abstract:
Provided is a method of exactly calculating the delay of a gate in a digital integrated circuit (IC) that drives a capacitive load and a noise current source based on a crosstalk effect due to capacitive coupling between adjacent conductive lines, the method calculates the delay of the gate by using an output waveform that sums an output waveform of a linear time-varying output resistance model generated by using a gate output resistance library generated by using input and output voltage values of the digital IC and an output waveform of a modified Thevenin equivalent model of the gate.
Public/Granted literature
- US20100299114A1 METHOD OF CALCULATING GATE DELAY BASED ON CROSSTALK EFFECT DUE TO CAPACITIVE COUPLING Public/Granted day:2010-11-25
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