Invention Grant
- Patent Title: Troubleshooting temporal behavior in “combinational” circuits
- Patent Title (中): 排除“组合”电路中的时间行为
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Application No.: US11942234Application Date: 2007-11-19
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Publication No.: US08271257B2Publication Date: 2012-09-18
- Inventor: Johan de Kleer
- Applicant: Johan de Kleer
- Applicant Address: US CA Palo Alto
- Assignee: Palo Alto Research Center Incorporated
- Current Assignee: Palo Alto Research Center Incorporated
- Current Assignee Address: US CA Palo Alto
- Agency: Fay Sharpe LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method and computer product is provided to generate a signal model for use in analyzing a model system including imposing an explicit time assumption for each time instant of the system model. The time assumptions are defined so that any two assumptions contradict each other, thereby separating all inferences into the respective times. A non-monotonic rule is applied to instantiate component models of the model system. Results are defined as not depending on the existence of a previous time instant and, a simplified signal model is generated, wherein the signal model represents the evolution of a value in the model system over time.
Public/Granted literature
- US20080294415A1 TROUBLESHOOTING TEMPORAL BEHAVIOR IN "COMBINATIONAL" CIRCUITS Public/Granted day:2008-11-27
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