Invention Grant
- Patent Title: Automatic circuit design technique using pareto optimal solutions
- Patent Title (中): 自动电路设计技术采用帕累托最优解
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Application No.: US12888700Application Date: 2010-09-23
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Publication No.: US08271921B2Publication Date: 2012-09-18
- Inventor: Izumi Nitta , Yu Liu
- Applicant: Izumi Nitta , Yu Liu
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Fujitsu Patent Center
- Priority: JP2009-219920 20090925
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A set of pareto optimal solutions that are non-dominated solutions in a solution specification space for respective items in requirement specification is extracted with a combination of a circuit configuration including a specific function and a process constraint condition. Furthermore, pareto optimal solutions are extracted for all combinations of the circuit configuration and the process constraint condition, and pareto optimal solutions are extracted for the respective process constraint conditions. When such extracted data is distributed to designers, it is possible to reduce time to generate the pareto optimal solutions, and the designers can design the optimum circuit having a desired function by using such extracted data.
Public/Granted literature
- US20110239182A1 AUTOMATIC CIRCUIT DESIGN TECHNIQUE Public/Granted day:2011-09-29
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