Invention Grant
US08271925B2 Printed board design system and method including decoupling capacitor arrangement examination unit 有权
印刷电路板设计系统及方法,包括去耦电容布置检查单元

  • Patent Title: Printed board design system and method including decoupling capacitor arrangement examination unit
  • Patent Title (中): 印刷电路板设计系统及方法,包括去耦电容布置检查单元
  • Application No.: US12628350
    Application Date: 2009-12-01
  • Publication No.: US08271925B2
    Publication Date: 2012-09-18
  • Inventor: Naoki Kobayashi
  • Applicant: Naoki Kobayashi
  • Applicant Address: JP Tokyo
  • Assignee: NEC Corporation
  • Current Assignee: NEC Corporation
  • Current Assignee Address: JP Tokyo
  • Priority: JP2008-306250 20081201
  • Main IPC: G06F17/50
  • IPC: G06F17/50
Printed board design system and method including decoupling capacitor arrangement examination unit
Abstract:
A decoupling capacitor pin position information obtain unit calculates based on board design data of a printed board, position information indicating positions of decoupling capacitors on the printed board. A power supply plane position/shape information obtain unit calculates based on the board design data, position/shape information indicating a position and shape of a power supply plane of the printed board. A restriction condition input unit collects restriction conditions from an input device. A decoupling capacitor examination unit judges based on the position information, the position/shape information and the restriction conditions, whether or not arrangement of the decoupling capacitors is adequate. Therefore, a designer, while designing arrangement/wiring of the printed board, can check in real time whether or not the arrangement of the decoupling capacitors is adequate, and thus can design at higher speed a printed board in which arrangement of decoupling capacitors is adequate.
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