Invention Grant
- Patent Title: Semiconductor integrated circuit with multi-cut via and automated layout method for the same
- Patent Title (中): 半导体集成电路采用多通孔和自动布局方式相同
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Application No.: US13137461Application Date: 2011-08-17
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Publication No.: US08271926B2Publication Date: 2012-09-18
- Inventor: Keiichi Nishimuda
- Applicant: Keiichi Nishimuda
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2007-74005 20070322
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L23/522

Abstract:
A semiconductor integrated circuit includes a first wiring formed on a first wiring layer and prolonged in a first direction, a second wiring formed on a second wiring layer and prolonged in a second direction, a third wiring formed on the first wiring layer and prolonged in the first direction, a fourth wiring formed on the second wiring layer and prolonged in the second direction, a multi-cut via formed to connect the first wiring to the second wiring, the multi-cut via including a first via and a second via formed in the first direction, and a single-cut via formed to connect the third wiring to the fourth wiring. A first overhang is provided in a direction opposite to the first direction, the first overhang being larger than a second overhang, the second overhang being smaller than a third overhang.
Public/Granted literature
- US20110304055A1 Semiconductor integrated circuit with multi-cut via and automated layout method for the same Public/Granted day:2011-12-15
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