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US08271932B2 Hierarchical error injection for complex RAIM/ECC design 有权
复杂RAIM / ECC设计的分层错误注入

Hierarchical error injection for complex RAIM/ECC design
Abstract:
A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined.
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