Invention Grant
- Patent Title: Semiconductor module
- Patent Title (中): 半导体模块
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Application No.: US12727565Application Date: 2010-03-19
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Publication No.: US08274148B2Publication Date: 2012-09-25
- Inventor: Yasuyuki Yanase , Atsunobu Suzuki , Yoshio Okayama
- Applicant: Yasuyuki Yanase , Atsunobu Suzuki , Yoshio Okayama
- Applicant Address: JP Osaka
- Assignee: Sanyo Electric Co., Ltd.
- Current Assignee: Sanyo Electric Co., Ltd.
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2009-110919 20090430
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52

Abstract:
A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding.
Public/Granted literature
- US20100276800A1 SEMICONDUCTOR MODULE Public/Granted day:2010-11-04
Information query
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