Invention Grant
US08274829B2 Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/− 10V BVDS
失效
行解码器和源解码器结构适用于在+/- 10V BVDS以下操作的NOR型闪存的页面，扇区和芯片单元中的擦除
- Patent Title: Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/− 10V BVDS
- Patent Title (中): 行解码器和源解码器结构适用于在+/- 10V BVDS以下操作的NOR型闪存的页面，扇区和芯片单元中的擦除
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Application No.: US12455936Application Date: 2009-06-09
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Publication No.: US08274829B2Publication Date: 2012-09-25
- Inventor: Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
- Applicant: Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
- Applicant Address: US CA San Jose
- Assignee: Aplus Flash Technology, Inc.
- Current Assignee: Aplus Flash Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman; Billy Knowles
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C11/4193
Abstract:
An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices.
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