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US08275956B2 Parallel memory device rank selection 有权
并行存储设备等级选择

Parallel memory device rank selection
Abstract:
A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules).
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