Invention Grant
- Patent Title: Parallel memory device rank selection
- Patent Title (中): 并行存储设备等级选择
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Application No.: US13168455Application Date: 2011-06-24
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Publication No.: US08275956B2Publication Date: 2012-09-25
- Inventor: Lidia Warnes , Teddy Lee , Ricardo Ernesto Espinoza-Ibarra , Dennis Carr , Michael Bozich Calhoun
- Applicant: Lidia Warnes , Teddy Lee , Ricardo Ernesto Espinoza-Ibarra , Dennis Carr , Michael Bozich Calhoun
- Applicant Address: US TX Houston
- Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee Address: US TX Houston
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F13/28

Abstract:
A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules).
Public/Granted literature
- US20110258400A1 PARALLEL MEMORY DEVICE RANK SELECTION Public/Granted day:2011-10-20
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