A data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a plurality of synchronization circuits for capturing and transmitting the data in response to a clock signal and a plurality of combinational circuits arranged between the synchronization circuits for processing the data, the plurality of synchronization circuits being arranged in at least two groups; an error detecting circuit for determining if the data input to one of the plurality of synchronization circuits is stable during a predetermined time and for signalling an error if the data input is unstable, the predetermined time being less than a half cycle of the clock signal; control circuitry responsive to said error detecting circuit signalling said error to transmit a control signal to at least one of said groups of synchronization circuits that contains a subsequent synchronization circuit that said synchronization circuit with said unstable input is configured to transmit said data to; each of said group of synchronization circuits being configured to respond to receipt of said control signal to stall for a clock cycle and to transmit a stall signal to at least one further group of synchronization circuits that said group of synchronization circuits is configured to transmit data to or receive data from; each of said group of synchronization circuits being configured to respond to receipt of said stall signal provided they have not stalled in a preceding clock cycle to stall for a clock cycle and to transmit a stall signal to said at least one further group of synchronization circuits.