Invention Grant
US08278121B2 Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis
有权
使用电化学合成在图案化晶片上制造聚合物阵列的方法和装置
- Patent Title: Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis
- Patent Title (中): 使用电化学合成在图案化晶片上制造聚合物阵列的方法和装置
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Application No.: US13242127Application Date: 2011-09-23
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Publication No.: US08278121B2Publication Date: 2012-10-02
- Inventor: Valery M. Dubin , Florian Gstrein , Gordon D. Holt , Brandon Barnett
- Applicant: Valery M. Dubin , Florian Gstrein , Gordon D. Holt , Brandon Barnett
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Pillsbury Winthrop Shaw Pittman LLP
- Agent Raj S. Dave
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
Public/Granted literature
- US20120070930A1 METHOD AND APPARATUS TO FABRICATE POLYMER ARRAYS ON PATTERNED WAFERS USING ELECTROCHEMICAL SYNTHESIS Public/Granted day:2012-03-22
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