Invention Grant
US08278171B2 Fabrication method for semiconductor device having laminated electronic conductor on bit line 有权
在位线上具有层叠电子导体的半导体器件的制造方法

  • Patent Title: Fabrication method for semiconductor device having laminated electronic conductor on bit line
  • Patent Title (中): 在位线上具有层叠电子导体的半导体器件的制造方法
  • Application No.: US13081777
    Application Date: 2011-04-07
  • Publication No.: US08278171B2
    Publication Date: 2012-10-02
  • Inventor: Kenichi FujiiMasahiko Higashi
  • Applicant: Kenichi FujiiMasahiko Higashi
  • Applicant Address: US CA Santa Clara
  • Assignee: Spansion LLC
  • Current Assignee: Spansion LLC
  • Current Assignee Address: US CA Santa Clara
  • Priority: WOPCT/JP2005/009878 20050530
  • Main IPC: H01L21/336
  • IPC: H01L21/336
Fabrication method for semiconductor device having laminated electronic conductor on bit line
Abstract:
There are provided a semiconductor device and a fabrication method therefor including an ONO film (18) formed on a semiconductor substrate (10), a word line (24) formed on the ONO film (18), a bit line (20) formed in the semiconductor substrate (10), and a conductive layer (32) that is in contact with the bit line (20), runs in a length direction of the bit line (20), and includes a polysilicon layer or a metal layer. In accordance with the present invention, a semiconductor device and a fabrication method therefor are provided wherein degradation of the writing and erasing characteristics and degradation of the transistor characteristics such as a junction leakage are suppressed, and the bit line resistance is decreased.
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