Invention Grant
- Patent Title: Stressed barrier plug slot contact structure for transistor performance enhancement
- Patent Title (中): 用于晶体管性能提升的阻塞插塞槽接触结构
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Application No.: US13306607Application Date: 2011-11-29
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Publication No.: US08278718B2Publication Date: 2012-10-02
- Inventor: Kevin J. Fischer , Vinay B. Chikarmane , Brennan L. Peterson
- Applicant: Kevin J. Fischer , Vinay B. Chikarmane , Brennan L. Peterson
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238

Abstract:
A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.
Public/Granted literature
- US20120068273A1 STRESSED BARRIER PLUG SLOT CONTACT STRUCTURE FOR TRANSISTOR PERFORMANCE ENHANCEMENT Public/Granted day:2012-03-22
Information query
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