Invention Grant
US08278752B2 Microelectronic package and method for a compression-based mid-level interconnect
有权
用于基于压缩的中级互连的微电子封装和方法
- Patent Title: Microelectronic package and method for a compression-based mid-level interconnect
- Patent Title (中): 用于基于压缩的中级互连的微电子封装和方法
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Application No.: US12646854Application Date: 2009-12-23
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Publication No.: US08278752B2Publication Date: 2012-10-02
- Inventor: Brent M. Roberts , Mihir K. Roy , Sriram Srinivasan , Sridhar Narasimhan
- Applicant: Brent M. Roberts , Mihir K. Roy , Sriram Srinivasan , Sridhar Narasimhan
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H01L23/48
Abstract:
A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.
Public/Granted literature
- US20110147913A1 MICROELECTRONIC PACKAGE AND METHOD FOR A COMPRESSION-BASED MID-LEVEL INTERCONNECT Public/Granted day:2011-06-23
Information query
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