Invention Grant
- Patent Title: Semiconductor integrated circuit and method for manufacturing same, and mask
- Patent Title (中): 半导体集成电路及其制造方法及掩模
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Application No.: US11783962Application Date: 2007-04-13
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Publication No.: US08278760B2Publication Date: 2012-10-02
- Inventor: Yoshihisa Matsubara
- Applicant: Yoshihisa Matsubara
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Young & Thompson
- Priority: JP2006-113609 20060417
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L29/40
Abstract:
A semiconductor integrated circuit includes a first conductor provided in a first region on a substrate and a second conductor provided in a second region on the substrate. The second region is a region enclosing the first region. A minimum design dimension in linewidth of the first conductor is smaller than a minimum design dimension in linewidth of the second conductor.
Public/Granted literature
- US20070241329A1 Semiconductor integrated circuit and method for manufacturing same, and mask Public/Granted day:2007-10-18
Information query
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