An input attenuator may include a first input circuit having an RF_IN+ terminal, a first node, a transmission line, a DC blocking capacitor, a second node, a third node, and an output terminal coupled in series, the first node selectively coupled to ground via a serially coupled capacitor and a first silicon germanium heterojunction bipolar transistor, the second node coupled to ground via a capacitor, and the third node selectively coupled to ground via a DC blocking capacitor, a resistor, and a second silicon germanium heterojunction bipolar transistor coupled in series. The input attenuator may also include a second input circuit parallel to the first input circuit and having structure similar to the first input circuit.