A Complex Analog to Digital Converter System on Chip (CADC SoC) implemented into a microcircuit system is provided. A series of stagger clock signals can be fixed on either a rising or falling edge of the system clock and a plurality of A/D converters can be grouped by sets (i.e. odd and even) and assigned to odd or even stagger clocks. A complex I&Q data manager is provided for controlling the system. A clock management system is responsive to an external signal to select from a set of stagger clock settings, thereby improving anti-alias performance.