Invention Grant
US08279208B2 Driving circuit of matrix device, matrix device, image display device, electrophoretic display device, and electronic apparatus
有权
矩阵装置,矩阵装置,图像显示装置,电泳显示装置和电子装置的驱动电路
- Patent Title: Driving circuit of matrix device, matrix device, image display device, electrophoretic display device, and electronic apparatus
- Patent Title (中): 矩阵装置,矩阵装置,图像显示装置,电泳显示装置和电子装置的驱动电路
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Application No.: US12552414Application Date: 2009-09-02
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Publication No.: US08279208B2Publication Date: 2012-10-02
- Inventor: Yasuhiro Shimodaira
- Applicant: Yasuhiro Shimodaira
- Applicant Address: JP Tokyo
- Assignee: Seiko Epson Corporation
- Current Assignee: Seiko Epson Corporation
- Current Assignee Address: JP Tokyo
- Agency: AdvantEdge Law Group, LLC
- Priority: JP2008-253422 20080930
- Main IPC: G06F3/038
- IPC: G06F3/038 ; G09G5/00

Abstract:
A driving circuit is provided which is applied to a matrix device having a plurality of functional elements arranged in a matrix, which is connected to the functional elements via data lines, and which has a plurality of blocks. The driving circuit includes a shift register which has a plurality of register sections, each of the register sections being corresponding to one of the plurality of blocks; a data signal line; a first data latch circuit connected to an output terminal of the shift register and the data signal line; and a second data latch circuit connected to the output terminal of the shift register and an output terminal of the first data latch circuit, and connected to the data line directly or via another circuit. The first and second data latch circuits are respectively divided into multistage operation units. Each of the operation units is corresponding to the one data line or the plurality of data lines and is corresponding to one of the plurality of blocks. An output terminal of the shift register belonging to a block B is connected to the operation unit of the first data latch circuit belonging to the block B, the output terminal of the shift register belonging to a block A is connected to the operation unit of the second data latch circuit belonging to the block B, and each of the block A and block B is one of the plurality of blocks.
Public/Granted literature
Information query
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