Invention Grant
- Patent Title: Integrated circuit design method for improved testability
- Patent Title (中): 集成电路设计方法，提高可测性
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Application No.: US12453930Application Date: 2009-05-27
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Publication No.: US08279230B2Publication Date: 2012-10-02
- Inventor: Takashi Nose , Hirobumi Furihata
- Applicant: Takashi Nose , Hirobumi Furihata
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-140179 20080528
- Main IPC: G09G5/00
- IPC: G09G5/00
Abstract:
A display device is provided with a display panel; and a display panel driver driving the display panel in response to externally-provided image data. The display panel driver includes a display memory for storing the image data, and is configured to perform overdrive processing on the image data read from the display memory. The display panel driver includes an overdrive processing control circuit detecting writing of the image data into the display memory to control operation and halt of a circuit used for the overdrive processing.
Public/Granted literature
- US20090295813A1 Integrated circuit design method for improved testability Public/Granted day:2009-12-03
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