Invention Grant
US08279692B2 Semiconductor device having hierarchical data line structure and control method thereof 有权
具有分层数据线结构及其控制方法的半导体器件

  • Patent Title: Semiconductor device having hierarchical data line structure and control method thereof
  • Patent Title (中): 具有分层数据线结构及其控制方法的半导体器件
  • Application No.: US12910496
    Application Date: 2010-10-22
  • Publication No.: US08279692B2
    Publication Date: 2012-10-02
  • Inventor: Yoshinori Matsui
  • Applicant: Yoshinori Matsui
  • Applicant Address: JP Tokyo
  • Assignee: Elpida Memory, Inc.
  • Current Assignee: Elpida Memory, Inc.
  • Current Assignee Address: JP Tokyo
  • Agency: Sughrue Mion, PLLC
  • Priority: JP2009-244390 20091023
  • Main IPC: G11C7/00
  • IPC: G11C7/00
Semiconductor device having hierarchical data line structure and control method thereof
Abstract:
To provide a semiconductor device including switch transistor provided between a sub-data line and a main data line. Upon transferring data, the semiconductor device supplies a potential of a VPP level to a gate electrode of the switch transistor when causing the switch transistor to be a conductive state, and supplies a potential of a VPERI level to the gate electrode when causing the switch transistor to be a non-conductive state. According to the present invention, because a potential of the gate electrode is not decreased to a VSS level when causing the switch transistor to be a non-conductive state, it is possible to reduce a current required to charge and discharge a gate capacitance of the switch transistor. Furthermore, because the VPP level is supplied to the gate electrode when causing the switch transistor to be a conduction state, a level of a signal after transfer never drops down by the amount of the threshold voltage.
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