A first periodic signal generation circuit generates first periodic output signals. A second periodic signal generation circuit generates second periodic output signals. A first multiplexer circuit receives the first and the second periodic output signals. An interface circuit coupled to external pins generates a third periodic output signal based on a periodic signal selected by the first multiplexer circuit. A second multiplexer circuit receives the third periodic output signal at an input. A first periodic feedback signal provided to the first periodic signal generation circuit is based on a signal selected by the second multiplexer circuit. A third multiplexer circuit receives the third periodic output signal at an input. A second periodic feedback signal provided to the second periodic signal generation circuit is based on a signal selected by the third multiplexer circuit.