Invention Grant
- Patent Title: Pattern verification method, pattern verification apparatus, and pattern verification program
- Patent Title (中): 模式验证方法,模式验证装置和模式验证程序
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Application No.: US12700820Application Date: 2010-02-05
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Publication No.: US08280147B2Publication Date: 2012-10-02
- Inventor: Mitsufumi Naoe , Toru Miyauchi , Tomoyuki Okada , Seiji Makino , Koichi Suzuki , Masakazu Ohseki
- Applicant: Mitsufumi Naoe , Toru Miyauchi , Tomoyuki Okada , Seiji Makino , Koichi Suzuki , Masakazu Ohseki
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2009-63322 20090316
- Main IPC: G06K9/00
- IPC: G06K9/00

Abstract:
A pattern verification apparatus includes a correction section creating a plurality of first data pieces; a determination section performing light intensity simulation to create a plurality of plots, determine whether or not each of the plurality of simulation result plots falls within an allowable range, and recognize two or more simulation result plots which do not fall within the allowable range as a plurality of second data pieces; an extraction section extracting a reference pattern of the plurality of original design patterns corresponding to the plurality of second data pieces; and a classifying section classifying the plurality of second data pieces into categories of the reference pattern.
Public/Granted literature
- US20100232679A1 PATTERN VERIFICATION METHOD, PATTERN VERIFICATION APPARATUS, AND PATTERN VERIFICATION PROGRAM Public/Granted day:2010-09-16
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