Invention Grant
US08280713B2 Automatic generation of test suite for processor architecture compliance
有权
自动生成用于处理器架构合规性的测试套件
- Patent Title: Automatic generation of test suite for processor architecture compliance
- Patent Title (中): 自动生成用于处理器架构合规性的测试套件
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Application No.: US11735510Application Date: 2007-04-16
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Publication No.: US08280713B2Publication Date: 2012-10-02
- Inventor: Allon Adir , Sigal Asaf , Laurent Fournier , Itai Jaeger
- Applicant: Allon Adir , Sigal Asaf , Laurent Fournier , Itai Jaeger
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455

Abstract:
A parametrically controlled model-based test generator automatically generates architectural compliance test suites for different implementations of a processor architecture, based on a set of architectural decisions chosen among optional behaviors for each implementation. Thus, different implementations of the same architecture can be easily supported by modifying the parameter values. In addition, ongoing changes to the architecture or comprehensive updates to the test suite can be easily handled by updating the architecture model or the coverage models, forgoing the need to review the whole, potentially huge, set of tests.
Public/Granted literature
- US20080255822A1 Automatic Generation of Test Suite for Processor Architecture Compliance Public/Granted day:2008-10-16
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