Invention Grant
- Patent Title: Packed restricted floating point representation and logic for conversion to single precision float
- Patent Title (中): 封装的限制浮点表示和逻辑转换为单精度浮点数
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Application No.: US11648265Application Date: 2006-12-29
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Publication No.: US08280936B2Publication Date: 2012-10-02
- Inventor: Hong Jiang
- Applicant: Hong Jiang
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F7/00
- IPC: G06F7/00 ; G06F15/00 ; G06F7/38 ; H03M7/00
Abstract:
An apparatus for expanding an immediate vector of restricted data structures may include logic connected to a first memory and a second memory connected to the logic. The first memory may store the immediate vector of restricted data structures that specify distinct floating point numbers. The immediate vector may have a fixed number of bits. The logic may expand the vector of restricted data structures into a number of corresponding expanded data structures that also specify the distinct floating point numbers. Each of the expanded data structures may also have the fixed number of bits. The second memory may store the number of corresponding expanded data structures.
Public/Granted literature
- US20100257221A1 Packed restricted floating point representation and logic for conversion to single precision float Public/Granted day:2010-10-07
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